Functional blocks in semiconductor integrated circuits are often designed with the assumption that all inputs to the block arrive simultaneously together. That is, the design of the functional block assumes that the all input signals to the block are valid, steady state signals at the same time with respect to a clock signal. In many cases, this is an incorrect assumption because the input signals into functional blocks often arrive at different times.
The design of a function block may require three or more input signals be evaluated simultaneous to produce a resultant output. However, the time spent waiting for the input signals to be valid at the input to the functional block is often not considered and leads to an unexpected increase in the delay of signals through the functional block. It is desirable to consider the input signal timing during the synthesis of the logic of functional blocks in integrated circuits.